System for selecting a task to be executed according to an output from a task control circuit

ABSTRACT

The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of co-pending application Ser. No.15/098,992, filed on Apr. 14, 2016, which is Continuation of co-pendingapplication Ser. No. 12/281,333, filed on Oct. 13, 2009, now patented asU.S. Pat. No. 9,342,350 on 17 May 2016, which is a U.S. National Stageof International Application No. PCT/JP2006/316655, filed Aug. 24, 2006,for which priority is claimed under 35 U.S.C. §120, the entire contentsof all of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to the function of an operating systemand, more particularly, to task scheduling technology.

2. Description of the Related Art

Operating systems for dedicated devices such as cell phones, as well asoperating systems for general-purpose devices such as personalcomputers, are required to perform advanced functions on a growingscale. Particularly, an operating system capable of executing aplurality of tasks by a single central processing unit (CPU)(hereinafter, an OS of this type will be referred to as a multitask OS)is now built in a large number of electronic devices.

A multitask OS divides the processing time of a CPU into units of time(time slices) and assigns time slices to a plurality of tasks. Each taskis allowed to use the CPU only while being assigned a time slice fromthe OS. A single task can be executed in a given time slice. Since atime slice is a very short period of time, it looks to a user as if theplurality of tasks is being executed at the same time. According to sucha method of processing, the processing power of the CPU is effectivelyused by giving the right for execution to task B when task A reaches astate to wait for an input and thus no longer needs the computing powerof the CPU. The term “right for execution” is synonymous with the rightto use the CPU.

Transfer of the right for execution by the multitask OS will be referredto as a task switch. A task switch occurs when a time slice expires orwhen a task executes a predetermined instruction. A multitask OS savescontext information of a task being executed in a task control block(TCB) when a task switch is to be executed. Context information is datarelated to data stored in a register of the CPU while the task is beingexecuted or data related to the state of execution. A TCB is an areareserved in a memory to store information unique to a task. A multitasksaves context information of a task being executed in a TCB, thenselects a task to give the right for execution to, reads contextinformation from the TCB for the selected task, and loads theinformation into a CPU register. In this way, each task continues itsprocess step by step in units of time slices.

While a multitask OS has the advantage of being capable of executing aplurality of tasks efficiently, it also involves a disadvantage ofincurring the overhead associated with saving and loading contextinformation. Normally, the advantage of a multitask OS far surpasses theoverhead associated with a task switch.

Recently, real-time operating systems with severe requirements forcompletion of a process within a predefined period of time are beingused extensively especially in embedded systems. In an RTOS with severetime requirements, overhead incurred in a task switch may affect theperformance of the system as a whole significantly. We have come torealize that overhead associated with a task switch must be reduced inorder to facilitate more efficient multitasking.

SUMMARY OF THE INVENTION

A general purpose of the present invention is to provide a technologyadapted for multitasking whereby execution of tasks can be controlledmore efficiently than in the related art.

One aspect of the present invention relates to a task processor. Theprocessor comprises a processing register, an execution control circuitoperative to load data from a memory into the processing register andexecutes a task in accordance with the data in the processing register,a plurality of save registers respectively associated with a pluralityof tasks, and a task control circuit.

In executing a predetermined system call instruction, the executioncontrol circuit notifies the task control circuit accordingly.

Upon being notified of the execution of a system call instruction, thetask control circuit switches tasks for execution by saving, in the saveregister associated with the task being executed, the data in theprocessing register, selecting a task to be executed next, and loadingthe data in the save register associated with the selected task into theprocessing register.

The data loaded into the processing register may include: an instructionand an operand; an instruction without an operand; or simple data suchas a program counter or a stack pointer. According to the methodprocessing, context information can be saved and loaded by swappingcontext information between the save registers associated with therespective tasks and the processing register used for execution. As thiseliminates the need to access a TCB to save and load data from and intothe processing register, high-speed task switching can be achieved.

Optional combinations of the aforementioned constituting elements, andimplementations of the invention in the form of methods, systems,recording mediums, and computer programs may also be practiced asadditional modes of the present invention. Accordingly, the execution oftasks can be controlled more efficiently in multitasking.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a state transition diagram of a task;

FIG. 2 is a conceptual diagram of a commonly used RTOS;

FIG. 3 is a circuit diagram of a commonly used CPU in which a softwareRTOS is executed;

FIG. 4 is a conceptual diagram of the RTOS;

FIG. 5 is a circuit diagram of the task processor;

FIG. 6 is a circuit diagram of the CPU of FIG. 5;

FIG. 7 is a circuit diagram showing how the execution control circuithalts the CPU clock;

FIG. 8A is a time chart showing the relation between signals when aninterrupt request signal occurs;

FIG. 8B is a time chart showing the relation between signals when asystem call is executed;

FIG. 9 schematically shows the timing of halting the CPU clock in apipeline process;

FIG. 10 is a circuit diagram showing the relation between the statestorage units and the task switching circuit;

FIG. 11 shows a task ready list used by a commonly used RTOS to select aRUN-task;

FIG. 12 is a circuit diagram of the execution selection circuit;

FIG. 13 shows a wait semaphore list used in a semaphore processperformed by a commonly used RTOS;

FIG. 14 is a circuit diagram of the semaphore-based selection circuit;

FIG. 15 is a state transition diagram of the task switching circuit;

FIG. 16 is a circuit diagram showing a variation to the task processorof FIG. 5 in which the task control circuit is not provided; and

FIG. 17 is a circuit diagram showing a variation to the task processorof FIG. 5 in which the save circuit is not provided.

DETAILED DESCRIPTION

A task processor 100 according to an embodiment of the present inventionimplements the task scheduling function of a multitask OS by anelectronic circuit. Before describing the details of the task processor100, a description will be given of state transition of a task withreference to FIG. 1. The description hereunder is directed to statetransition of a task in a commonly used multitask OS. However, theillustration is equally applicable to state transition of a task in thetask processor 100. An overview of a system call executed in the taskprocessor 100 will also be given. The design concept of a commonly usedmultitask OS will be described with reference to FIGS. 2 and 3 and themethod of processing in the task processor 100 according to theembodiment will be described in detail with reference to FIGS. 4 through10. The features of the task processor 100 in connection with processesrelated to semaphores, mutexes, and events will also be discussed bycomparing the inventive features with the technology commonly used.

[State Transition of a Task]

FIG. 1 is a state transition diagram of a task. In a multitask process,each task has a state. Each task makes a transition between a pluralityof states and is in a certain state at any given point of time. A statetransition is triggered by execution of a system call or detection of aninterrupt request signal. A system call is a special instruction amongthe instructions executed by a task. An interrupt request signal occurswhen certain data is received from a peripheral device (e.g., in theevent of depression of a key of the keyboard, a mouse click, orreception of data communicated from elsewhere). A state transition alsooccurs when a time slice assigned to a task has been consumed.

Tasks are categorized into ordinary tasks and special tasks. Ordinarytasks are non-special tasks executed in response to a system call.Special tasks are tasks executed in response to detection of aninterrupt request signal. Special tasks are alternatively referred to asinterrupt handlers. The states that a task can assume will be describedfirst and then a description will be given of various system callinstructions.

(1) STOP State (Sleep State)

In the STOP state, a task remains inactive. Both ordinary tasks andspecial tasks can assume the STOP state. Hereinafter, tasks in the STOPstate will be referred to as STOP-tasks.

1-1. Ordinary Tasks

When a task executes a system call directing activation of another task(hereinafter, referred to as an activation system call), an ordinarytask in the STOP state makes a transition to the READY state describedlater.

1-2. Special Tasks

A special task is normally in the STOP state. When a task switchingcircuit 210 described later detects an interrupt request signal, aspecial task makes a transition from the STOP state to the RUN state.The task formerly in the RUN state makes a transition to the READYstate.

(2) RUN State (Execution State)

In the RUN state, a task is being executed. In other words, a task hasbeen assigned a time slice and has acquired the right to use the CPU.Both ordinary tasks and special tasks can assume the RUN state.Hereafter, tasks in the RUN state will be referred to as RUN-tasks. Of aplurality of tasks, only one can assume the RUN state. No two tasks canassume the RUN state concurrently.

2-1. Ordinary Tasks

Upon executing a predetermined system call, an ordinary task in the RUNstate makes a transition from the RUN state to the READY state or theWAIT state described later. Transition to the READY state also occurswhen a task in the RUN state has consumed a time slice. Whichever is thecase, an ordinary task formerly in the READY state makes a transition tothe RUN state in place of the task formerly in the RUN state. Upondetection of an interrupt request signal, the RUN-task makes atransition to the READY state. In this process, a special task formerlyin the STOP state makes a transition to the RUN state. When the RUN-taskexecutes a system call (hereinafter, referred to as a termination systemcall) for terminating the execution of itself, the RUN-task makes atransition to the STOP state.

2-2. Special Tasks

A special task, upon making a transition from the STOP state to the RUNstate in response to an interrupt request signal, returns to the STOPstate upon completion of its process. A special task may only assume theSTOP state and the RUN state.

(3) READY State (Executable State)

In the READY state, a task can be executed. A task in the READY state isready to make a transition to the RUN state once given an authority forexecution from the OS. Only ordinary tasks can assume the READY state.Hereinafter, tasks that are in the READY state will be referred to asREADY-tasks.

When an ordinary task formerly in the RUN state makes a transition to astate other than the RUN state as a result of the execution of a systemcall, or when a special task in the RUN state makes a transition to theSTOP state upon completion of its process, a READY-task makes atransition to the RUN state to take the place of the task formerly inthe RUN state. Ordinary tasks make a transition to the RUN state onlyfrom the READY state. When there are a plurality of tasks in the READYstate, one of the READY-tasks makes a transition to the RUN state basedupon the task order priority, which forms context information. Whenthere are a plurality of READY-tasks assigned the same task priorityorder, the task with the oldest history of transition to the READY statemakes a transition to the RUN state.

(4) WAIT State (Standby State)

In the WAIT state, a task waits for the fulfillment of a WAITcancellation condition. When the WAIT cancellation condition isfulfilled, the task in the WAIT state makes a transition to the READYstate. Only ordinary tasks can assume the WAIT state. Hereinafter, tasksthat are in the WAIT state will be referred to as WAIT-tasks. The WAITcancellation condition will be described in detail later.

To summarize, tasks can continue their process using the CPU only whenthe task is in the RUN state. An RTOS manages the state of a pluralityof tasks to switch between RUN-tasks as appropriate. This will allow theCPU to execute at least one of the tasks at any given point of time.

[System Call]

An additional description will be given of a system call. System callsare largely categorized into three types: calls related activation;calls related to WAIT; and calls related to SET.

(1) System Calls Related to Activation

System calls related to activation are calls related to transitionbetween the STOP state and the READY state.

1-1. Activation System Call

An activation system call is a call whereby task A, a RUN-task,activates another ordinary task B. In the event of an activation systemcall, task B in the STOP state makes a transition to the READY state.

1-2. Termination System Call

The task that has executed this system call terminates its process andmakes a transition from the RUN state to the STOP state. A terminationsystem call may be an instruction whereby a given task causes anothertask to terminate its process.

(2) System Calls Related to WAIT

System calls related to WAIT are calls related to transition between theRUN state and the WAIT state.

2-1. Wait Semaphore System Call

A system call that requires acquisition of a semaphore (describedlater).

2-2. Wait Mutex System Call

A system call that requires acquisition of a mutex (described later).

2-3. Wait Event System Call

A system call that waits for the establishment of an event (describedlater). For execution, a wait event system call accepts an event ID, await flag pattern (described later), and a flag condition (describedlater) as parameters.

Whichever is the case, system calls related to WAIT establish variousWAIT cancellation conditions. When the WAIT cancellation condition isalready fulfilled when a system call related to WAIT is executed, theRUN-task that has executed the system call makes a transition to theREADY state. Meanwhile, when the WAIT cancellation condition is notfulfilled, the RUN-task makes a transition to the WAIT state in whichthe task waits for the fulfillment of the WAIT cancellation condition.

(3) System Calls Related to SET

System calls related to SET are calls related to transition between theWAIT state and the READY state. Execution of a system call related toSET triggers the establishment of the WAIT cancellation condition.

3-1. Release Semaphore System Call

A system call that releases a semaphore.

3-2. Release Mutex System Call

A system call that releases a mutex.

3-3. Set Event System Call

A system call that establishes a current flag pattern (described later)of an event.

3-4. Clear Flag System Call

A system call that clears the current flag pattern to zero.

The description of the embodiment assumes the use of the nine types ofsystem calls listed above. It goes without saying, however, that variousother system calls can be implemented.

[Design Concept of Commonly Used RTOS]

FIG. 2 is a conceptual diagram of a commonly used RTOS.

The illustrated RTOS is a multitask OS.

A commonly used RTOS is implemented as software. Switching of a RUN-taskfrom task A to task B will be described by way of example. Since task Ais occupying the CPU, the RTOS generates an interrupt to the CPU so asto seize the right to use the CPU from task A. Thereupon, the RTOS savesthe context information of task A in a TCB. The RTOS selects task B asthe next RUN-task and loads the context information from the TCB fortask B into a register of the CPU. When the load is complete, the RTOSdelivers the right to use the CPU to task B. In this way, the RTOSperforms a task switch from task A to task B by temporarily acquiringthe right to use the CPU. The same is true of the execution of specialtasks. As in the case of ordinary tasks, the RTOS achieves a task switchby saving the context information of a RUN-task in a TCB beforedelivering the right to use the CPU to a special task.

Since the RTOS is implemented by software, the RTOS needs the right touse the CPU in order to execute its process. In other words, the RTOSand the tasks contend with each other in respect of the right to use theCPU. Hereinafter, an RTOS implemented by software will be referred to asa software OS.

FIG. 3 is a circuit diagram of a commonly used CPU in which a softwareRTOS is executed.

A CPU 84 includes an execution control circuit 90 for controlling memoryaccess, instruction execution, etc. in an integrated manner, and aprocessing register set 92 for storing various data such as contextinformation of tasks, and an operator circuit 94 for arithmeticoperation. The processing register set 92 is a set of a plurality oftypes of registers and is largely categorized into special registers 88and general-purpose registers 86. Special registers 88 are registers forstoring a program counter, a stack pointer, and a flag, etc.General-purpose registers 86 are registers for storing work data andinclude a total of 16 registers R0-R15. While the special registers 88are put to both the user's use and the system's use (dual planes), thegeneral-purpose registers 86 is only put to a single use (single plane).Hereinafter, data stored in the processing register set 92 will bereferred to as process data.

The execution control circuit 90 uses a control signal (CTRL) directedto an output selector 98 to output the process data in a desiredregister, of the processing register set 92, to the operator circuit 94.The operator circuit 94 performs an arithmetic operation by referring tothe process data, i.e., instructions and variables. The result ofoperation is output to an input selector 96. The execution controlcircuit 90 uses a control signal (CTRL) directed to the input selector96 to feed a result of operation to a desired register of the processingregister set 92.

The execution control circuit 90 also reads data from a memory via theCPU bus and loads the data into the processing register set 92 via theinput selector 96. Further, the execution control circuit 90 records theprocess data in the memory via the CPU data bus. The execution controlcircuit 90 executes a task, while updating the program counter in thespecial registers 88.

In the event of a task switch, the execution control 90 saves processdata in a TCB, an area reserved in the memory. It will be assumed thattask A executes a system call and a task switch from task A to task Boccurs. The RTOS acquires the right to use the CPU, triggered by theexecution of a system call. This causes the CPU 84 to be temporarilyoperated in accordance with the program of the RTOS. The processingsteps are as follows.

<Saving of Context Information of Task A>

1. The execution control circuit 90 performs switching so as to put thespecial registers 88 to the system's use instead of the user's use.Process data subject to the RTOS process is loaded into the specialregisters 88 put to the system's use.

2. The execution control circuit 90 saves the data in thegeneral-purpose registers 86 in a stack (not shown).

3. The execution control circuit 90 loads the process data for the RTOSfrom a recording medium (not shown) (e.g., another register) into thegeneral purpose registers 86.

At this stage, the process data in the process register set 92 iscompletely replaced by the process data for the RTOS.

4. The RTOS identifies the TCB for task A in the memory and writes theprocess data saved in the stack in the TCB. The process data in thespecial registers 88 put to the user's use is also written in the TCB aspart of the context information. In this way, the process data for taskA is saved in the TCB. The RTOS indicates in the TCB for task A thattask A has made a transition from RUN to READY (or WAIT).

<Loading of Context Information of Task B>

1. The RTOS identifies the TCB for task B in the memory and writes thecontext information in the TCB in the stack and in the special registers88 put to the user's use. The RTOS indicates in the TCB for task B thattask B has made a transition from the READY to the RUN.

2. The RTOS removes the data for the RTOS process from thegeneral-purpose registers 86 and saves the same in a recording medium(not shown).

3. The execution control circuit 90 loads the context information in thestack into the general-purpose registers 86. The execution controlcircuit 90 performs switching so as to put the special registers 88 tothe user's use instead of the system's use. In this way, the processdata for task B is loaded into the process register set 92.

A task switch is achieved through the processing steps as describedabove. Normally, each of the general purpose registers 86 comprises asingle plane and as such uses a stack in order to switch between theprocess data for a task and the process data for the RTOS. If thegeneral-purpose registers 86 are provided with two planes, there will beno need to save and load data via a stack. This will allow a task switchto take place at a higher speed.

The embodiment achieves even faster task switching by providing saveregisters 110 for respective tasks. A task switch using the saveregisters 110 will be described in detail with reference to FIG. 5. Itwill be learned that, in the case of the CPU 84 and the commonly usedsoftware RTOS described with reference to FIG. 3, accesses to the TCBoccurs frequently for a task switch. An assumption in the exampledescribed above is that a task switch from task A to task B occurs. Inpractice, however, a large number of instructions should be executed inorder for the RTOS to select task B. This process also involves frequentaccesses from the RTOS to the memory. The task processor 100 accordingto the embodiment enables faster task switching by using a task controlcircuit 200 (described later) dedicated to task selection.

[Hardware Implementation of RTOS by the Task Processor 100]

FIG. 4 is a conceptual diagram of the RTOS according to the embodiment.

Unlike a commonly used software RTOS, the RTOS according to theembodiment is primarily implemented by hardware separate from the CPU.Hereinafter, the RTOS implemented by hardware will be referred to ashardware RTOS. Since the RTOS according to the embodiment is primarilyconfigured as hardware separate from the CPU, it hardly needs the rightto use the CPU for its processing. In other words, the RTOS and the taskdo not contend with each other in respect of the right to use the CPU.In the case of the commonly used software RTOS shown in FIG. 2, the CPUserves as a task execution circuit and an RTOS execution circuit. Incontrast, in the case of the hardware RTOS according to the embodiment,the CPU is clearly defined as a task execution circuit. The taskscheduling function is primarily implemented by a save circuit 120 andthe task control circuit 200 described later.

FIG. 5 is a circuit diagram of the task processor 100 according to theembodiment.

The task processor 100 includes the save circuit 120 and the taskcontrol circuit 200 in addition to a CPU 150. The CPU 150 is an entityresponsible for the execution of a task. The save circuit 120 and thetask control circuit 200 are responsible for playing the role of theRTOS shown in FIG. 4. Task scheduling is performed primarily under thecontrol of the task control circuit 200.

The CPU 150 includes an execution control circuit 152, a processingregister set 154, and an operator circuit 160. The CPU 150 may be anordinary CPU as described with reference to FIG. 3. The difference isthat signal lines in the CPU 150 according to the embodiment areconnected in a manner different from those of the CPU 84 shown in FIG.3. The specific circuit configuration will be described in detail withreference to FIG. 6.

The task control circuit 200 includes a task switching circuit 210, asemaphore table 212, an event table 214, a task selecting circuit 230,and state storage units 220. The semaphore table 212 and the event table214 will be described in detail with reference to FIG. 13 and subsequentdrawings. The state storage units 220 are units associated withrespective tasks. Hereinafter, a state storage unit 220 associated withtask A is denoted as a state storage unit 220_A. The same is true of theother units 220. Each state storage unit 220 stores state data of theassociated task. State data represents information indicating theattributes (e.g., task priority order, task state, etc.) of a task andforming a part of context information. The specific details of the datawill be described later with reference to FIG. 10. The state storageunits 220 continuously output the state data of the tasks to the taskselecting circuit 230. The task selecting circuit 230 selects a task(e.g., a RUN-task) on the basis of the state data of the tasks. The taskselecting circuit 230 will be described in detail with reference to FIG.10 and subsequent drawings. The task switching circuit 210 performs atask switch when detecting a system call signal (SC) received from theexecution control circuit 152 or an interrupt request signal (INTR) froman external device and thereupon.

When a system call is to be executed, the execution control circuit 152transmits a system call signal (SC) to the task switching circuit 210.When the task switching circuit 210 detects an interrupt request signal(INTR), the task switching circuit 210 asserts a halt request signal(HR) sent to the execution control circuit 152. While the operation ofthe CPU 150 is halted, the execution control circuit 152 asserts a haltcompletion signal (HC) sent to the task switching circuit 210. Thesethree signals allow the CPU 150 and the task control circuit 200 to beoperated in coordination.

The save circuit 120 includes a load selection circuit 112 and aplurality of save registers 110. The save registers 110 are also unitsassociated with the respective tasks and are used to save process datain the processing register set 154. Therefore, the save registers 110have a data capacity equal to or greater than that of the processingregister set 154. Hereinafter, the save register 110 associated withtask A is denoted as a save register 110_A. The same is true of theother registers 110. The load selection circuit 112 is directed by thetask switching circuit 210 to load the data in one of the save registers110 (hereinafter, the data stored in the save register 110 will bereferred to as saved data) into the processing register set 154.

Each save register 110 continuously outputs the respective saved data tothe load selection circuit 112. When the task switching circuit 210feeds a task selecting signal (TS) designating a task ID, the loadselection circuit 112 outputs the saved data in the save register 110associated with the designated task to the processing register set 154.Further, when the task switching circuit 210 feeds a write signal (WT)to the processing register set 154, the saved data is actually loadedinto the processing register set 154.

Meanwhile, the entirety process data in the processing register set 154is also continuously output to the save registers 110. When the taskswitching circuit 210 asserts a write signal (WT) sent to the desiredsave register 110, the processing data is saved in the save register110. The number of bits transferable in one sitting by the busconnecting the processing register set 154 and the save registers 110 isdefined so as to enable parallel transfer of process data. Therefore,the task switching circuit 210 is capable of writing process data in thesave registers 110 in one sitting merely by transmitting a write signalonce to the save registers 110. The number of bits of the bus connectingthe save registers 110 and the load selection circuit 112 and the busconnecting the load selection circuit 112 and the CPU 150 are alsodefined similarly.

Hereinafter, the methods of performing a task switch in response to asystem call and in response to an interrupt request signal will bedescribed.

[1] Execution of System Call

When the execution control circuit 152 of the CPU 15 executes a systemcall, the execution control circuit 152 halts the clock of the CPU 150(hereinafter, referred to as CPU clock (CLK)). The specific method ofhalting will be described in detail with reference to FIG. 7, etc. Theexecution control circuit 152 transmits a system call signal (SC)indicating the execution of a system call to the task switching circuit210 of the task control circuit 200. When the halt of the CLK iscompleted, the execution control circuit 152 asserts a halt completionsignal (HC) sent to the task switching circuit 210.

Nine signal lines connect the CPU 150 and the task switching circuit 210for transfer of system call signals. The nine signal lines areassociated with the nine types of system calls described before. Theexecution control circuit 152 transfers a digital pulse via one of thesystem signal lines in accordance with the type of system call executed.The task switching circuit 210 is immediately capable of detecting thetype of system call executed by the identifying the system signal lineson which the digital pulse is detected. The task switching circuit 210selects necessary data from the data output from the task selectingcircuit 230 in accordance with the type of system call and executes theprocess designated by the system call. The process is executed on thecondition that HC is asserted. The relation between the task switchingcircuit 210 and the task selecting circuit 230 will be described indetail with reference to FIG. 10. The parameter and return value of thesystem call are written in predetermined general-purpose registers 158of the processing register set 154. The task switching circuit 210 iscapable of reading the parameter from the general-purpose registers 158and writing the return value in the registers 158. It will be assumedhere that task A, a RUN-task, executes a wait semaphore system call. Theprocess data for task A need be saved first.

<Saving of Context Information of Task A>

The execution control circuit 152 feeds a SC signal indicating a waitsemaphore system call to the task switching circuit 210. The executioncontrol circuit 152 halts CLK and asserts HC when the halt is completed.The task switching circuit 210 outputs the semaphore ID of the semaphoreto be waited for to a semaphore-based selection circuit 234 (describedlater), which forms the individual selecting circuits built in the taskselecting circuit 230, and the selects task B to be executed next. Thetask switching circuit 210 writes necessary data in the state storageunit 220_A. For example, the circuit 210 updates the state of task A,switching from RUN to READY or WAIT. More specifically, the taskswitching circuit 210 outputs state data indicating the task state WAITto all of the state storage units 220 and thereupon feeds a write signalWT_A only to the state storage unit 220_A. In this way, the state oftask A is updated.

Subsequently, the task switching circuit 210 outputs a write signal (WT)to the save register 110_A. Since the process data in the processingregister set 154 is continuously output to the save registers 110, thewrite signal (WT) causes the process data for task A to be saved in thesave register 110_A for task A.

<Loading of Context Information of Task B>

When the updating of the state data of task A and saving of the processdata for task A are completed, the task switching circuit 210 outputs atask selecting signal (TS_B) designating task B to the load selectioncircuit 112. This causes the saved data in the save register 110_B to beoutput to the processing register set 154. When the task switchingcircuit 210 outputs a write signal (WT) to the processing register set154, the saved data for task B is loaded into the processing registerset 154. The task switching circuit 210 also writes necessary data inthe state storage unit 220 for task B. For example, the circuit 210updates the state of task B, switching from READY to RUN. When the aboveprocess is completed, the execution control circuit 152 resumes the CPUclock. The CPU 15 starts executing task B according to the resumed CPUclock. The further details of the processing method will be describedwith reference to FIG. 8B.

[2] Generation of Interrupt Request Signal

The task switching circuit 210 detects an interrupt request signal(INTR) from a peripheral device. More specifically, the interruptrequest signal (INTR) is transmitted from an interrupt controller (notshown) to the task switching circuit 210. The parameter indicating thelevel of the interrupt request signal is recorded in a register built inthe interrupt controller. The task switching circuit 210 asserts a haltrequest signal (HR) sent to the execution control circuit 152, whereuponthe execution control circuit 152 halts the CPU clock. As in the processinitiated by the execution of a system call, the task switching circuit210 saves the process data for the RUN-task in the save register 110.Subsequently, the task switching circuit 210 activates a special task.Only one type of special task is available for activation irrespectiveof the parameter of the interrupt request signal. The special task readsthe parameter of INTR from the register built in the interruptcontroller and performs a process according to the parameter. Theprocess performed by the special task may be the execution of a setevent system call or a semaphore system call, or the process may be theactivation of an ordinary task. Depending on the parameter, the specialtask may be terminated without executing any specific process. Whatprocess is executed according to the parameter of INTR depends on theimplementation of the special task. When the execution of the specialtask is completed, the next RUN-task is selected from among theREADY-tasks.

The task switching circuit 210 loads the process data in the saveregister 110 associated with the special task into the CPU 150. Timerequired to switch from an ordinary task to a special task can beestimated from the operation clock of the task control circuit 200. Whena predetermined number of operation clocks is counted since HR isasserted and sent to the execution control circuit 152, the taskswitching circuit 210 negates HR in order to cancel the halt of the CPUclock. When HR is negated, the execution control circuit 152 resumes theCPU clock. At this point of time, the task switching circuit 210 hascompleted the task switch from an ordinary task to a special task. Thespecific details of the processing method will be described later withreference to FIG. 8A.

In either case, core processes involved in a task switch, i.e.,(A)saving and loading of process data and (B) task state transition andselection of a RUN-task are implemented in hardware. Elimination of aneed to access a TCB on the memory in (A) and (B) additionallycontributes to increase of speed in a task switch. What is required inthe CPU 150 of the task processor 100 is to additionally include thefunction of halting and resuming the CPU clock. The scope of the presentinvention is not limited to the complete hardware implementation ofthese functions. For example, a skilled person would readily appreciatethat the primary function of (A) or (B) may be implemented in hardwareand a part of the function of the RTOS may be implemented in software inorder to assist the hardware function.

FIG. 6 is a circuit diagram of the CPU 150 of FIG. 5.

Unlike the CPU 84 of FIG. 3, the special registers 156 and thegeneral-purpose registers 158 of the processing register set 154 areboth of a single-plane configuration. Introduced in the processingregister set 154 are an input bus from the load selection circuit 112,an output bus to the save registers 110, and a signal line for a writesignal (WT) from the task switching circuit 210. The execution controlcircuit 152 uses a control signal (CTRL) directed to an output selector164 to feed the data in a desired register, of the processing registerset 92, to the operator circuit 160. The result of operation representsan input to the input selector 162. The execution control circuit 152uses a control signal (CTRL) directed to the input selector 162 to feedthe result of operation to a desired register of the processing registerset 154. The execution control circuit 152 executes a task, whileupdating the program counter in the special registers 156.

The process data is not saved in the TCB on the memory but in the saveregisters 110. The processing register set 154 continuously outputs theprocess data to the save registers 110. The point of time at which theprocess data is saved in the save registers 110 is controlled by thetask switching circuit 210 as described previously.

The saved data is loaded into the processing register set 154 not fromthe TCB on the memory but from the save registers 110. The determinationof a save register 110 from which to load the process data and thetiming of load are controlled by the task switching circuit 210 asdescribed previously.

The number of bits transferable by the bus connecting the processingregister set 154 and the load selection circuit 112 and the busconnecting the processing register set 154 and the save registers 110are defined so as to enable parallel transfer of process data in onesitting. Thus, data can be read or written in one sitting in response toa write signal (WT) from the task switching circuit 210. An ordinarysoftware RTOS need occupy the processing register set 154 temporarilyfor task switching. In contrast, the hardware RTOS according to theembodiment need not load special process data into the processingregister set 154 for a task switch. What is only required for taskswitch from task A to task B is to save the process data for task A andthen load the process data for task B. Accordingly, there is no need toconfigure the processing register set 154 to comprise two planes or toswap data via a stack.

FIG. 7 is a circuit diagram showing how the execution control circuit152 halts the CPU clock.

The original clock (CLK0) and the output of a first AND gate 172 are fedto a second AND gate 174. The output of the gate 172 is inverted beforebeing provided to the gate 174. The output of the first AND gate 172 isa halt completion signal (HC). Since the halt completion signal (HC) isnormally zero, the second AND gate 174 outputs the input original clock(CLK0) as the CPU clock (CLK) unmodified. The CPU 150 operates byreceiving the CPU clock output by the second AND gate 174. When theoutput of the first AND gate 172 is 1, i.e., when the halt completionsignal (HC)=1, the output of the second AND gate 174 is fixed at zero sothat the CPU clock (CLK) is halted.

The output of an OR gate 176 and a CPU busy signal (CBUSY) are fed tothe first AND gate 172. The CPU busy signal is inverted before beingprovided to the gate 172. CBUSY is a signal output from a known statemachine that generates an internal cycle of the CPU 150. When the CPU150 can be halted, CBUSY becomes 1. For example, when the operatorcircuit 94 has executed a single instruction or the last of a pluralityof instructions being locked and the CPU can be halted accordingly, orwhen the supply of the CPU clock is already halted, CBUSY becomes 0.

The output of an instruction decoder 170 (SC_DETECT) and a halt requestsignal (HR) from the task switching circuit 210 are fed to the OR gate176. The instruction decoder 170 has a built-in latch circuit forlatching SC_DETECT. The instruction decoder 170 receives data (FD)fetched from the CPU 150. When FD is a system call instruction, thedecoder 170 outputs SC_DETECT=1. The built-in latch circuit ensures thatthe instruction decoder 170 continues to output SC_DETECT=1 even if FDchanges subsequently. A write signal (WT) sent from the task switchingcircuit 210 to the processing register set 154 is also fed to theinstruction decoder 170. When WT changes from 0 to 1, the saved data isloaded into the processing register set 154, as described previously. WTis a pulse signal that returns from 1 to 0 after a predetermined periodof time. When WT changes from 1 to 0, the latch circuit of theinstruction decoder 170 is reset and the instruction decoder 170 negatesSC_DETECT. The relation between SC_DETECT and the write signal (WT) willbe described in detail with reference to FIG. 8B. The instructiondecoder 170 according to the embodiment is a device exclusively providedin the execution control circuit 152 in order to determine whether aninstruction subject to execution is a system call. In a variation to theembodiment, the instruction decoder 170 and the CPU decoder responsiblefor the decoding stage of the CPU 150 may be implemented in the samehardware. In this case, the instruction decoder 170 can be implementedby adding to the CPU decoder the function of outputting SC_DETECT=1 whenthe decoded data is a system call instruction.

When an interrupt request signal (INTR) occurs, the task switchingcircuit 210 asserts a halt request signal (HR) sent to the executioncontrol circuit 152. In other words, the output of the OR gate 176 goes1 when a system call is executed or when a halt request signal (HR) isasserted.

To summarize, when a system call is executed or an interrupt requestsignal occurs, and when the CPU busy signal goes 0, the output of thefirst AND gate 172 goes 1 and the second AND gate 174 discontinuesoutputting the CPU clock.

FIG. 8A is a time chart showing the relation between signals when aninterrupt request signal occurs.

Referring to FIG. 8A, the task switching circuit 210 detects aninterrupt request signal (INTR) from an external device at time t0. Thetask switching circuit 210 asserts a halt request signal (HR) sent tothe execution control circuit 152 in order to allow execution of aspecial task. Time t1, when the signal HR is input, substantiallyconcurs with time t0 when the interrupt is detected. At time t1, thestate machine of the CPU 150 indicates that a task is being executed sothat CBUSY=1. Since HR=1, the OR gate 176 outputs 1. However, the CPU150 is not halted since CBUSY=1. Therefore, even if HR=1 is fed, the CPUclock (CLK) in synchronization with the original clock (CLK0) is outputfor a time.

As time elapses, CBUSY goes 0 at time t2.

Since HR=1 already, the first AND gate 172 outputs HC=1. The CPU clockoutput from the second AND gate 174 is fixed at 0. Meanwhile, the taskswitching circuit 210 initiates a task switch from an ordinary task to aspecial task, triggered by the assertion of HC. Details will bedescribed later. Time required for a task switch includes several clocksfor operating the task control circuit 200. The task control circuit 200negates the halt request signal (HR) on the condition that the operationclock for the task control circuit 200 changes a predetermined number oftimes (time t3) since the assertion of HC. Since HR=0, the executioncontrol circuit 152 resumes the CPU clock (CLK). When the CPU 150resumes its process, the CPU 150 changes CBUSY from 0 to 1 (time t4).Thus, in a period from time t2 to time t3, while the CPU clock ishalted, a task switch from an ordinary task to a special task isperformed.

In an alternative method of processing, HR may be negated on thecondition that the task switching circuit 200 has completed a taskswitch instead of on the condition that the operation clock for the taskcontrol circuit 200 changes a predetermined number of times. Theexecution control circuit 152 may negate HC on the condition that HR isnegated. The execution control circuit 152 resumes the CPU clock (CLK)when HC=0. The execution of the task may be resumed accordingly.

FIG. 8B is a time chart showing the relation between signals when asystem call is executed.

Referring to FIG. 8B, the instruction decoder 170 detects a system calland changes SC_DETECT from 0 to 1 at time t0. At time t0, the statemachine of the CPU 150 indicates that the task is being executed so thatCBUSY=1. Since SC_DETECT=1, the OR gate 176 outputs 1. However, sinceCBUSY=1, the CPU 150 is not halted. Therefore, even if SC_DETECT=1 isoutput, the CPU clock (CLK) in synchronization with the original clock(CLK0) is output for a time.

As time elapses, CBUSY goes 0 at time t1. Since SC_DETECT=1 and CBUSY=1,HC is negated and the CPU clock is halted. When HC=0 is fed, the taskswitching circuit 210 initiates a task switch and outputs a write signal(WT) to the CPU 150. At time t2, when WT goes from0 to 1, the saved datais loaded into the processing register set 154. Since a write signal(WT) is a pulse signal, WT goes 0 at time t3 after an elapse of apredetermined time. Detection of a falling edge of WT (WT:1−>0) causesSC_DETECT latched in the instruction decoder 170 to be reset (time t4).At this point of time, CBUSY changes from 0 to 1. Since CBUSY=1, HC=0 sothat the CPU clock is resumed. Thus, in a period from time t1 to timet4, while the CPU clock is halted, a task switch is performed.

In an alternative method of processing, HC may be negated on thecondition that the task switching circuit 200 has completed a taskswitch and negated HR instead of on the condition that a falling edge ofWT (WT:1−>0) is detected. SC_DETECT is reset on the condition that HC=0.The execution control circuit 152 resumes the CPU clock (CLK) and CBUSYgoes from 0 to 1.

In any case, the CPU 150 need not have knowledge that the RUN-task isswitched while the CPU clock is halted. The task switching circuit 210performs a task switch while the CPU clock is halted so that the CPU 150is “frozen”. Therefore, the process in the CPU 150 and the process inthe task switching circuit 200 are isolated from each other in thesequence of events.

FIG. 9 schematically shows the timing of halting the CPU clock in apipeline process.

The CPU 150 executes a task by executing a plurality of instructions,reading them sequentially from the memory into the processing registerset 154. Execution of an instruction as a unit of execution of a task isdecomposed into the following four phases.

1. F (fetch): the instruction is retrieved from the memory.

2. D (decode): the instruction is decoded.

3. E (execution): the instruction is executed.

4. WB (write back): the result of execution is written in the memory.

When a given task sequentially executes instructions 1 through 5,instruction 1 may be allowed to go through stages F through WB and theninstruction 2 may be allowed to go through stage F. However, forefficient execution, the execution of instruction 2 is started duringthe execution of instruction 1 in a majority of cases. Such a method ofprocessing is called pipeline processing. For example, when instruction1 reaches phase D, phase F of instruction 2 is started. When instruction1 reaches phase E, phase D of instruction 2 and phase F of instruction 3are initiated. Thus, the execution time of each task can be reduced byincreasing the number of instructions executed per unit time.

Each phase may be further divided into two small phases. For example,phase F may be divided into two phases F1 an F2. When instruction 1reaches phase F2, phase F1 of instruction 2 is started. When instruction1 reaches phase D1, phase F2 of instruction 2 and phase F1 ofinstruction 3 are started. By segmenting a phase, the computingresources of the CPU 150 can be used more efficiently. Referring to FIG.9, a description will be given of the timing of halting the CPU clockwhen a system call is generated in a pipeline process whereby each phaseis segmented into two phases for execution.

Referring to FIG. 9, instruction 1 is started to be processed at time 0defined by the CPU clock. At time 4 defined by the CPU clock, decodingof instruction 1 is completed. It will be assumed that instruction 1 isa system call. The instruction decoder 170 changes SC_DETECT from 0to 1. SC_DETECT returns from 1 to 0 on the condition that the writesignal from the task switching circuit 210 to the processing registerset 154 changes from 1 to 0. Even if SC_DETECT=1 is output, CBUSYremains 1 since instructions 2 through 5 are already being executed.Therefore, the second AND gate 174 continues to output the CPU clock.Meanwhile, when SC_DETECT=1, the execution control circuit 152 suspendsthe update of the program counter so that no new instructions arefetched. Accordingly, instruction 6 and subsequent instructions are notfetched.

The execution of instruction 1 is completed at time 8 defined by the CPUclock, but instructions 2 through 5 are being executed. Therefore, theCPU busy signal remains 1. When time 12 defined by the CPU clock isreached, the execution of instruction 5 is completed. At this point oftime, the CPU busy signal goes 0. The supply of the CPU clock is haltedaccording to the process described with reference to FIG. 8B. The taskswitching circuit 210 saves the process data yielded upon completion ofthe execution of instruction 5 in the save registers 110. According tothe method of halting as described above, a task switch can take placein such a manner that the result of execution of instructions subsequentto the execution of a system call is not wasted. When the task switch iscompleted, the CPU busy signal is set to 1 again and the instructiondecoder 170 resumes its process. This resumes the supply of the CPUclock.

In an alternative method of processing, the CPU busy signal may be setto 0 at a point of time when the execution of a system call instructionis completed so that the supply of the CPU clock is halted. In thiscase, instructions that are executed concurrently with the system callinstruction are halted while being executed. The interim results ofprocessing the suspended instructions are recorded in the processingregister set 154 before being saved in the save registers 110. Theexecution of the suspended instructions is resumed when the taskgenerating these instructions is turned into a RUN-task subsequently.For example, when an instruction is fetched and then suspended at thatstage, instructions and operands read from the memory are saved in thesave registers 110. When the task is resumed, the data in the saveregisters 110 is loaded into the processing register set 154 so that thedecoding stage and the subsequent stages are executed.

FIG. 10 is a circuit diagram showing the relation between the statestorage unit 220 and the task switching circuit 210.

The state storage unit 220 includes a state register 250 and a timer252. The stage storage unit 220 stores the state data of a task. Thetimer 252 is started when a task makes a transition to the READY stateor to the WAIT state. Time elapsed since the transition of a task to theREADY state is referred to as elapsed READY time and time elapsed sincethe transition of a task to the WAIT state will be referred to aselapsed WAIT time. The timer 252 continuously outputs the value of theelapsed time as a TIM signal. When a task makes a transition to theREADY state or to the WAIT state in a task switch, the task switchingcircuit 210 drives the timer 252 for the task so as to start measuringtime.

The state storage unit 220 is a set of registers as described below.

(A) Task ID register 254: a register for storing a task ID. The task IDregister 254 continuously outputs an ID signal indicating a task ID tothe task selecting circuit 230. Hereinafter, the ID signal output fromthe task ID register 254 for task A to the task selecting circuit 230will be denoted as an ID_A signal. The same notation will be used forall the other signals output from the state storage unit 220.

(B) Task priority order register 256: a register for storing a taskpriority order. The task priority order register 256 continuouslyoutputs a PR signal indicating the priority order of a task. The largerthe value, the higher the priority of the task, 0 denoting the highestpriority.

(C) Task state register 258: a register for storing a task state. Theregister 258 continuously outputs an ST signal indicating one of theSTOP, RUN, WAIT, and IDLE states. An IDLE state occurs prior to theinitialization of a task.

(D) Task activation register 260: a register for storing the TCB addressof a task in the memory. The register 260 outputs an AD signal.

(E) Wait reason register 262: a register for storing the reason for waitwhile a task is in the WAIT state, the reason for wait forming a WAITcancellation condition.

The reasons for wait are as follows: “in wait for a semaphore”; “in waitfor an event”; and “in wait for a mutex”.

The register 260 outputs an AD signal.

The register 262 outputs a WR signal.

(F) Semaphore ID register 264: a register for storing the semaphore IDof a semaphore to wait for when a task is in the WAIT state for thereason that the task waits for a semaphore. The register 264 outputs anSID signal.

(G) Mutex ID register 265: a register for storing the mutex ID of amutex to wait for when a task is in the WAIT state for the reason thatthe task waits for a mutex. The register 264 outputs an MID signal.

(H) Even ID register 266: a register for storing the event ID of anevent to wait for when a task is in the WAIT state for the reason thatthe task waits for an event. The register 266 outputs an EID signal.

(I) Wait flag register 268: a register for storing a wait flag patternwhen a task is in the WAIT state for the reason that the task waits foran event. The register 268 outputs an FL signal.

(J) Flag condition register 270: a register for storing a flag conditionwhen a task is in the WAIT state for the reason that the task waits foran event. The register 270 outputs an FLC signal. A wait flag patternand a flag condition will be described in detail later.

(K) Flag initialization register 272: a register for storing dataindicating whether or not a wait flag pattern is established. Theregister 272 outputs an FLI signal.

(L) Timeout counter 274: a register for storing a timeout value. Atimeout value is a variable designated in system calls related to WAIT.The task switching circuit 210 decrements the timeout value of thetimeout counter 274 periodically. The counter 274 outputs a TO signal.Instead of allowing the task switching circuit 210 to decrement atimeout value, the time-out counter 274 may periodically decrement itstimeout value autonomously.

The task selecting circuit 230 selects a task on the basis of thesignals output from the state storage units 220. The task selectingcircuit 230 include the following circuits.

(A) Execution selection circuit 232: a circuit for selecting a nextRUN-task to effect a task switch. The execution selection circuit 232always selects one of the tasks on the basis of the state datacontinuously output from the state storage units 220. The executionselection circuit 232 receives four inputs ID, ST, PR, and TIM. Thecircuit outputs the task ID of the next RUN-task. The circuitconfiguration will be described in detail with reference to FIG. 12.

(B) Semaphore-based selection circuit 234: a circuit for selecting thetask to make a transition from the WAIT state to the READY state inresponse to the execution of a release semaphore system call. Thecircuit 234 receives the semaphore ID of the semaphore released by arelease semaphore system call (hereinafter, simply referred to as asemaphore to be released) from the task switching circuit 210. Thecircuit 234 receives six inputs ID, ST, WR, PR, SID, and TIM from thestate storage units 220. The output of the circuit 234 is the task ID ofthe task to make a transition from the WAIT state to the READY state. Inthe absence of the associated task, the circuit 234 outputs apredetermined value such as −1. The specific circuit configuration willbe described in detail with reference to FIG. 13.

(C) Event-based selection circuit 236: a circuit for selecting the taskto make a transition from the WAIT state to the READY state in responseto the execution of a set event system call. The circuit 236 receivesthe event ID of the event that is set by a set event system call(hereinafter, simply referred to as a set event) from the task switchingcircuit 210. The circuit 236 receives six inputs ID, ST, WR, EID, FL,and FLC from the state storage units 220. The output of the circuit 236is the task ID of the task to make a transition from the WAIT state tothe READY state and FL and FLC of the task.

(D) Timeout detecting circuit 238: a circuit for detecting a task, amongthe tasks in the WAIT state, for which the timeout value of the timeoutcounter 274 reaches zero. The timeout detecting circuit 238 is driveneach time the timeout value is updated. The circuit 238 receives threeinputs ID, ST, and TO. The circuit 238 outputs the task ID of theassociated task. In the absence of the associated task, the circuit 238outputs a predetermined value such as −1.

(E) Mutex circuit 240: a circuit for selecting the task to make atransition from the WAIT state to the READY state in response to theexecution of a release mutex system call. The circuit 240 receives themutex ID of the mutex released by a release mutex system call(hereinafter, simply referred to as a released mutex) from the taskswitching circuit 210. The circuit 240 receives six inputs ID, ST, WR,PR, SID, and TIM from the state storage units 220. The circuit 240outputs the task ID of the task to make a transition from the WAIT stateto the READY state. In the absence of the associated task, the circuit240 outputs a predetermined value such as −1.

(F) Retrieval circuit 242: a circuit that outputs the entire state dataof a task when the task ID thereof is received from the task switchingcircuit 210.

Hereinafter, a task switch will be described, highlighting the processof the task selecting circuit 230 and discussing the selection of aRUN-task, semaphore, event, mutex, and timeout in comparison with thecommonly used technology.

[Selection of a RUN-Task]

[1] Selection of a RUN-task by a Commonly Used Software RTOS

FIG. 11 shows a task ready list used by a commonly used RTOS to select aRUN-task.

A task ready list is formed on the memory, connecting the TCBs of theREADY-tasks by pointers. Priority order pointers 280 are provided forrespective task priority orders and indicate the start address of theTCB for the task having the associated task priority order. In the caseof the task ready list of FIG. 11, the priority order pointer 280 of thetask priority order 0 addresses the TCB for task A. The priority orderpointer 280 of the task priority order 1 addresses the TCB for task B.The TCB for task A addresses the TCB for task D.

A commonly used software RTOS scans the task ready list to select thenext RUN-task. In this process, the RTOS performs the following twosteps.

A. Cause a RUN-task to make a transition from RUN to READY.

B. Select the next RUN-task and causes the selected task to make atransition from READY to RUN.

The process performed by the software RTOS is decomposed into thefollowing.

<State Transition of a RUN-Task>

The description hereunder assumes that task I is the RUN-task.

A1. The RTOS stores the task ID of the RUN-task in the memory.

The RTOS acquires the address of the TCB for task I on the basis of thetask ID.

A2. The RTOS accesses the TCB to acquire the task priority order of taskJ. It will be assumed that the task priority order is 0.

A3. The RTOS refers to the task ready list shown in FIG. 11 to acquirethe priority order pointer 280 associated with the task priority orderof task J.

A4. The RTOS detects the TCB indicated by the priority order pointer 280thus acquired. In this case, the TCB for task A is detected.

A5. The RTOS follows the pointer leading from the TCB for task A so asto detect the

TCB at the end of the list. FIG. 11 shows that task F is at the end ofthe list.

A6: The RTOS configures the pointer from the TCB for task F to addressthe TCB for task J. In this way, the TCB for task J is added to the taskready list.

A7. The RTOS indicates in the TCB for task J that task J is in the READYstate. The process data is copied to the register storage area of theTCB.

<State Transition of a READY-Task>

B1. The RTOS detects whether the priority order pointer 280 of the taskpriority order 0 points to any TCB. In the absence of TCBs, RTOS detectswhether the priority order pointer 280 of the task priority 1 points toany TCB. The RTOS attempts to identify a task until a TCB pointed to isfound, while going through the list in the descending order of taskpriority. In the illustrated case, task A is identified.

B2. The RTOS removes task A from the task ready list. More specifically,the priority order pointer 280 of the task order 0 is rewritten so as toaddress the TCB for task D instead of task A. Further, the pointer oftask A is configured to NULL so as not to address task D. In this way,the TCB for task A is removed from the task ready list.

B3. The RTOS indicates in the TCB for task A that task A is in the RUNstate. Further, the process data saved in the register storage area ofthe TCB for task A is loaded into the processing register set.

A commonly used software RTOS performs a task switch by using the taskready list as described above. The following policies are observed whenthe RTOS selects a RUN-task from among a plurality of READY-tasks.

1. The task selected should be a READY-task (first condition).

2. The task selected should have the highest priority order among theREADY-tasks (second condition).

3. If there are a plurality of tasks assigned the highest task priorityorder, the task selected should have the oldest history of going intothe READY state (third condition).

These three conditions will be collectively referred to as a RUN-taskselection condition. The execution control circuit 232 of the taskprocessor 100 implements the RTOS's task scheduling function asdescribed above in hardware.

[2] Selection of a RUN-Task by the Hardware RTOS

FIG. 12 is a circuit diagram of the execution selection circuit 232.

The description hereunder assumes that a RUN-task is selected from amongeight tasks, namely task 0 through task 7. The execution selectioncircuit 232 includes four 1st comparison circuits 290 (290 a-290 d), two2nd comparison circuits 292 (292 a, 292 b), and a 3rd comparison circuit294. The circuit 232 also includes eight determination circuits 296 (296a-296 h). Each of the determination circuits 296 receives an ST signalindicating the task state. When the signal indicates READY, the circuit296 outputs a CID signal at 1. When the signal indicates a state otherthan READY, the circuit 296 outputs a CID signal at 0.

The determination circuit 296 performs a determination based upon thefirst condition of the RUN-task selection condition. Each of the firstcomparison circuits 290 receives ID, PR, and TIM of two tasks and alsoreceives the CID signal from the determination circuit 296.

The first comparison circuit 290 a will be described by way of example.The first comparison circuit 290 a compares task 0 and task 1 so as toselect the suitable of the two on the basis of the RUN task selectioncondition mentioned above.

First determination: the circuit 290 a compares the CID signals outputfrom the determination circuit 296 a and the determination circuit 296b, respectively. If one of the signals is 1, i.e., if only one of thetasks is in the READY state, the first comparison circuit 29 a outputsID, PR, and TIM of the task. If both of the signals are 0, i.e., ifneither of the tasks is in the READY state, the first comparison circuit290 a outputs ID=PR=TIM=NULL. This shows that none of the tasks isselected. If both of the signals are 1, i.e., if both of the tasks arein the READY state, the second determination is performed as describedbelow.

Second determination: the circuit 290 a compares the PR signal of task 0and the PR signal of task 1 so as to select the task with the highertask priority order. For example, given that the task priority order oftask 0 is 1 and the task priority order of task 1 is 2, the circuit 290a outputs ID, PR, and TIM of task 0. The second determination enablesselection of the RUN-task with the highest task priority order as acandidate for RUN-task. If the task priority order of task 0 is the sameas that of task 1, the third determination is performed as describedbelow.

Third determination: the circuit 290 a compares the TIM signal of task 0and the TIM signal of task 1 so as to select the task with the longerelapsed READY time. If the tasks are associated with the same elapsedREADY time, task 0 is selected. Since the determination is made only bycomparing the elapsed time, TCB order management such as that based on atask ready list is not necessary.

In this way, a pair of task 0 and task 1, a pair of task 2 and task 3, apair of task 4 and task 5, and a pair of task 6 and task 7 are subjectto comparison according to the RUN task selection condition. Each of thesecond comparison circuits 292 narrows down the candidates for RUN-taskby examining the output from the two 1st comparison circuits 290. Thesecond comparison circuit 292 a performs task selection by referring tothe outputs of the first comparison circuit 290 a and the firstcomparison circuit 290 b. Therefore, the second comparison circuit 292 aoutputs ID, PR, and TIM of the task that best matches the RUN taskselection condition from among task 0 through task 3. The thirdcomparison circuit 294 operates in a similar manner. The thirdcomparison circuit 294 outputs the task ID of one of task 0 through task7.

According to the method of processing as described above, the RUN taskselection condition can be implemented in hardware. A commonly usedsoftware RTOS selects a RUN-task by accessing a task ready list. Incontrast, the execution selection circuit 232 according to theembodiment selects a RUN-task by referring to the state datacontinuously output from the state storage units 220. The processperformed by the execution selection circuit 232 is summarized asfollows.

<State Transition of a RUN-Task>

The description hereunder assumes that task J is the RUN-task.

A1. The task switching circuit 210 indicates READY in the task stateregister 258 for task J.

A2. The task switching circuit 210 sets the timer 252 for task J so asto start measuring the elapsed READY time.

This causes task J to make a transition from RUN to READY. As describedpreviously, the process data is saved in the save register 110 for taskJ. The bus connecting the processing register set 154 and the saveregisters 110 is capable of transferring process data in parallel sothat the processes A1 and A2 can be performed in one clock.

<State Transition of a READY-Task>

B1. The task switching circuit 210 identifies the RUN-task by referringto the task ID output from the execution selection circuit 232 uponcompletion of the state transition of task J. The circuit 210 indicatesRUN in the task state register 258 for the identified task.

Thus, the identified task makes a transition from READY to RUN. Theprocess data for the identified task is loaded from the save registers110 into the processing register set 154. The bus connecting the saveregisters 110 and the processing register set 154 is also capable oftransferring process data in parallel so that the process of B1 can beperformed in one clock.

A software RTOS consumes more CPU clocks in a task switch due, forexample, to accesses to a task ready list. In contrast, the task controlcircuit 200 according to the embodiment is capable of completing a taskswitch in a far shorter period of time. Since the state storage units220 continuously output status data to the execution selection circuit232, the execution control circuit 232 continuously outputs the task IDof one of the tasks. Selection of a RUN-task is not started after a taskswitch is initiated. Instead, selection of a RUN-task is performedaccording to the output from the execution selection circuit 232occurring concurrently with a task switch. This adds to the speed of atask switch. The description above assumes that there are eight tasks. Alarger number of tasks can be addressed by increasing the number ofstages of comparison circuits.

[Semaphore Process]

FIG. 13 shows a wait semaphore list used in a semaphore processperformed by a commonly used RTOS.

A brief description will be given of a semaphore before describing await semaphore list. The semaphore table 212 records semaphore IDs andsemaphore counters in association with each other. Initially, a finitenumber is established in a semaphore counter. For example, it will beassumed that a semaphore ID=4 and a semaphore counter=3 are established.When one of the tasks executes a wait semaphore system call designatingthe semaphore with the semaphore ID=4 as a semaphore to wait for, thetask switching circuit 210 decrements the semaphore counter of thesemaphore to wait for. The semaphore counter is decremented each time await semaphore event call is issued to request acquisition. When thecounter reaches 0, the semaphore can no longer be acquired. The taskthat executes a wait semaphore system call designating a semaphore withthe semaphore counter at 0 as a semaphore to wait for makes a transitionto the WAIT state.

Meanwhile, when one of the tasks executes a release semaphore systemcall, designating the semaphore with the semaphore ID=4 as a semaphoreto be released, the task switching circuit 210 increments the semaphorecounter of the semaphore table 212.

In summary, when the semaphore counter>0, the task that executes a waitsemaphore system call makes a transition from RUN to READY. In thiscase, the semaphore counter is decremented.

When the semaphore counter=0, the task that executes a wait semaphoresystem call makes a transition from RUN to WAIT. The semaphore counteris not decremented.

In order for the task that executes a wait semaphore system call to makea transition from WAIT to READY, another task need execute a releasesemaphore system call.

[1] Semaphore Process by a Commonly Used Software RTOS

A commonly used software RTOS manages the TCBs of tasks in the WAITstate for the reason that the task waits for a semaphore (hereinafter,referred to as a task in wait for a semaphore) by using a wait semaphorelist. The wait semaphore list is a list having the configuration similarto that of the task ready list of FIG. 11 and is formed on the memory.The TCBs for the tasks in wait for a semaphore are connected bypointers. The priority order pointer 280 indicates the start address ofthe TCB for the task in wait for a semaphore having the associated taskpriority order.

When a release semaphore system call is executed, a commonly usedsoftware RTOS scans the wait semaphore list to select a task in wait fora semaphore to be placed from the WAIT state to the READY state. Thefollowing processes are performed by the RTOS when executing a waitsemaphore system call and when executing a release semaphore systemcall.

<Execution of a Wait Semaphore System Call>

The description hereunder assumes that task I is the RUN-task.

A1. The RTOS stores the task ID of the RUN-task in the memory. The RTOSacquires the address of the TCB for task J on the basis of the task ID.

A2. The RTOS detects the semaphore counter of the semaphore to wait fordesignated in a wait semaphore system call. Hereinafter, the processbranches according to the value of the semaphore counter.

(When the Semaphore Counter>0)

A3. The RTOS decrements the semaphore counter of the semaphore to waitfor.

A4. The RTOS indicates READY in the TCB for task J.

In this way, the TCB for task J is added to the task ready list.

(When the Semaphore Counter=0)

A3. The RTOS accesses the TCB to acquire the task priority order of taskJ. It will be assumed that the task priority order is 0.

A4. The RTOS refers to the wait semaphore list to acquire the priorityorder pointer associated with the task priority order of task J.

A5. The RTOS detects the TCB indicated by the priority order pointerthus acquired. In this case, the TCB for task A is detected.

A6. The RTOS follows the pointer leading from the TCB for task A so asto detect the TCB at the end of the list. FIG. 13 shows that task F isat the end of the list.

A7: The RTOS configures the pointer from the TCB for task F to addressthe TCB for task J. In this way, the TCB for task J is added to the waitsemaphore list.

A7. The RTOS indicates in the TCB for task J that task J is in the WAITstate. The RTOS also establishes the semaphore ID of the semaphore towait for.

<Execution of a Release Semaphore System Call>

B1. The RTOS sequentially follows the tasks with the task priority order0 so as to identify a task in wait for a semaphore to be released. Inthe absence of such a task, the RTOS searches for a task with the taskpriority order 1. The process branches depending on whether a task inwait for a semaphore to be released is identified.

(When the Task is Detected)

B2. The description hereunder assumes that task E is detected as such.The RTOS indicates in the TCB for task E that task E is in the READYstate. The RTOS also clears the semaphore ID of the semaphore to waitfor.

B3. The RTOS removes task E from the wait semaphore list.

B4. The RTOS causes the task that released the semaphore to make atransition from RUN to READY. The TCB for the task is added to the taskready list.

(When the Task is Not Detected)

B2. The RTOS increments the semaphore counter.

B3. The RTOS causes the task that released the semaphore to make atransition from RUN to READY. The TCB for the task is added to the taskready list.

A commonly used software RTOS performs a semaphore-related process bymanaging a wait semaphore list as described above. The followingpolicies are observed when the RTOS selects a READY-task from among aplurality of WAIT-tasks in releasing a semaphore.

1. The task selected should be a WAIT-task (first condition).

2. The task selected should be a WAIT-task in wait for a semaphore to bereleased (second condition).

3. If there are a plurality of such tasks, the task selected should havethe highest priority order (third condition).

4. If there are a plurality of tasks assigned the highest task priorityorder, the task selected should have the oldest history of going intothe WAIT state (fourth condition).

These four conditions will be collectively referred to as a semaphorewait cancellation condition. The semaphore-based selection circuit 234of the task processor 100 implements the RTOS's task scheduling functionas described above in hardware.

[2] Semaphore Process by the Hardware RTOS

FIG. 14 is a circuit diagram of the semaphore-based selection circuit234.

As in [1], the description assumes eight tasks, namely task 0 throughtask 7. The semaphore-based selection circuit 234 includes four 1stcomparison circuits 300 (300 a-300 d), two 2nd comparison circuits 302(302 a, 302 b), and a 3rd comparison circuit 304. The circuit 234 alsoincludes eight determination circuits 306 (306 a-306 h).

Each of the determination circuits 306 receives ST, WR, and SID signalsfrom the state storage units 220 and also receives a signal from thetask switching circuit 210 indicating a semaphore ID. The semaphore IDreceived is the semaphore ID of the semaphore to be released. Each ofthe determination circuits 306 outputs a CID signal at 1 if theassociated task is a task in wait for a semaphore to be released. Ifnot, the circuit 306 outputs a CID signal at 0. The determinationcircuit 306 outputs a result of determination based upon the first andsecond conditions of the semaphore wait cancellation condition. Each ofthe first comparison circuits 300 receives ID, PR, and TIM of two tasksand also receives the CID signal from the determination circuit 306.

The first comparison circuit 300 performs a determination based upon thethird and fourth conditions of the semaphore wait cancellationcondition. The same is true of the second comparison circuits 302 andthe third comparison circuit 304. As already made clear above, thesecond and third conditions of the RUN-task selection condition areidentical with the third and fourth conditions of the semaphore waitcancellation condition. The comparison circuits of the executionselection circuit 232 compare state data (PR, TIM) of tasks. Meanwhile,the comparison circuits of the semaphore-based selection circuit 234also compare state data (PR, TIM) of tasks. Thus, the first comparisoncircuits 290 of the execution selection circuit 232 and the firstcomparison circuits 300 of the semaphore-based selection circuit 234 arecircuits having the same logic built in. Therefore, the first comparisoncircuits may be implemented in the same hardware. Each task is subjectto determination by the determination circuit 306 on the basis of thefirst and second conditions, before being subjected to determination bythe first comparison circuit 300. Through the steps for determinationsimilar to those performed by the execution selection circuit 232, oneof the task IDs is output from the third comparison circuit 304. Thefollowing processes are performed when executing a wait semaphore systemcall and when executing a release semaphore system call.

<Execution of a Wait Semaphore System Call>

The description hereunder assumes that task I is the RUN-task.

A1. The task switching circuit 210 detects from the semaphore table 212the semaphore counter of the semaphore designated in a wait semaphoresystem call. Hereinafter, the process branches according to the value ofthe semaphore counter.

(When the Semaphore Counter>0)

A2. The task switching circuit 210 decrements the semaphore counter inthe semaphore table 212.

A3. The task switching circuit 210 indicates READY in the task stateregister 258 for task J. The task switching circuit 210 sets the timer252 for the RUN-task so as to start measuring the elapsed READY time.

(When the Semaphore Counter=0)

A2. The task switching circuit 210 indicates WAIT in the task stateregister 258 for task J, indicates “in wait for a semaphore” in the waitreason register 262, sets the semaphore ID of the semaphore to wait forin the semaphore ID register 264, and sets the timer 252 so as to startmeasuring the elapsed WAIT time.

The task that has executed the wait semaphore system call makes atransition from the RUN to READY or WAIT.

<Execution of a Release Semaphore System Call>

B1. The task switching circuit 210 feeds the semaphore ID of thesemaphore to be released to the determination circuits 306. Eachdetermination circuits 306 receiving the semaphore ID determines whetherthe first and second conditions of the semaphore wait cancellationcondition are fulfilled. Thus, the first comparison circuit 300 selectsa task on the basis of the third and fourth conditions.

(When One of the Determination Circuits Outputs 1 and the ThirdComparison Circuit 304 Outputs One of the Task IDs)

B2. The circuit 210 indicates READY in the task state register 258 forthe detected task, clears the wait reason register 262 and the semaphoreID register 264, and causes the timer 252 to start measuring the elapsedREADY time.

B3. The circuit 210 indicates READY in the task state register 258 forthe task that has executed the system call and starts measuring theelapsed READY time.

(When None of the Determination Circuits 306 Outputs 1 and the ThirdComparison Circuit 304 Does Not Output Any Task ID).

B2. The task switching circuit 210 increments the semaphore counter ofthe semaphore table 212.

B3. The circuit 210 causes the task that has executed the system call tomake a transition from RUN to READY.

Since the state storage units 220 continuously output status data to thesemaphore-based selection circuit 234, the semaphore-based selectioncircuit 234 can immediately perform selection when the task switchingcircuit 210 feeds a semaphore ID to the determination circuit 306.

[Mutex Process]

Like a semaphore, a mutex is used in synchronizing tasks. A mutex and asemaphore differ in the following respects.

1. An integer equal to or greater than 1 may be established in asemaphore counter. In contrast, a mutex is a special kind of semaphorewhere the count of the semaphore counter is 1 or 0. When the count ofthe semaphore counter is 2 or greater, two or more tasks can acquire thesame semaphore. However, only one task can acquire a given mutex.

2. The task capable of releasing a semaphore by a release semaphoresystem call is not necessarily the task that has acquired the semaphoreby a wait semaphore system call. In contrast, only the task that hasacquired a mutex by a wait mutex system call is capable of releasing themutex by a release mutex system call.

The following policies are observed when the circuit 210 selects aREADY-task from among a plurality of WAIT-tasks in releasing a mutex.

1. The task selected should be a WAIT-task (first condition).

2. The task selected should be a WAIT-task in wait for a mutex to bereleased (second condition).

3. If there are a plurality of such tasks, the task selected should havethe highest priority order (third condition).

4. If there are a plurality of tasks assigned the highest task priorityorder, the task selected should have the oldest history of going intothe WAIT state (fourth condition).

The four conditions will be collectively referred to as a mutex waitcancellation condition.

The following processes are performed by the hardware RTOS according tothe embodiment when executing a wait mutex system call and whenexecuting a release mutex system call. The semaphore table 212 stores amutex ID and occupation state data indicating whether the mutex isoccupied by any task, in association with each other. The occupationstate data is 0 when the mutex is not occupied. When the mutex isoccupied, the occupation state data is the task ID of the task occupyingthe mutex.

<Execution of a Wait Mutex System Call>

The description hereunder assumes that task J is the RUN-task.

A1. The task switching circuit 210 detects whether the mutex designatedin a wait mutex system call is occupied. Hereinafter, the processbranches according to whether the mutex is occupied.

(When the Mutex is Not Occupied)

A2. The task switching circuit 210 records, as occupation state data,the task ID of the task that has executed the system call.

A3. The circuit 210 indicates READY in the task state register 258 fortask J. The task switching circuit 210 sets the timer 252 for theRUN-task so as to start measuring the elapsed READY time.

(When the Mutex is Occupied)

A2. The task switching circuit 210 indicates WAIT in the task stateregister 258 for task J, indicates “in wait for a mutex” in the waitreason register 262, sets the mutex ID of the mutex to wait for in themutex ID register 265, and sets the timer 252 so as to start measuringthe elapsed WAIT time.

<Execution of a Release Mutex System Call>

B1. The task switching circuit 210 feeds the released semaphore ID tothe mutex circuit 240 on the condition that the task that has executedthe system call occupies the mutex to be released. The mutex circuit 240also includes comparison circuits connected in multiple stages as inFIG. 14 and determination circuits for determining whether the first andsecond conditions of the mutex wait cancellation condition arefulfilled. The determination circuit outputs 1 only when the first andsecond conditions of the mutex wait condition are both fulfilled withregard to the designated mutex. When a task not occupying the mutex tobe released executes a release mutex system call, the task is caused tomake a transition from RUN to READY.

(When one of the determination circuits outputs 1 and the mutex circuit240 outputs one of the task IDs)

B2. The circuit 210 indicates READY in the task state register 258 forthe detected task, clears the wait reason register 262 and the mutex IDregister 265, and causes the timer 252 to start measuring the elapsedREADY time.

B3. The circuit 210 indicates READY in the task state register 258 forthe task that has executed the system call and starts measuring theelapsed READY time.

(When none of the determination circuits 306 outputs 1 and the mutexcircuit 240 does not output any task ID).

B2. The task switching circuit 210 indicates that the mutex isunoccupied in the semaphore table 212.

B3. The circuit 210 causes the task that has executed the system call tomake a transition from RUN to READY.

[Event Process]

A brief description will now be given of event management according tothe embodiment. The event table records an event ID and a flag pattern(hereinafter, referred to as a current flag pattern) in association witheach other.

A flag pattern is an 8-bit pattern.

A set event system call is a system call for updating a current flagpattern, using an event ID and a flag pattern (hereinafter, referred toas a set flag pattern) as parameters. When a set event system call isexecuted, the current flag pattern of the associated event is updated toa logical sum of the current flag pattern and the set flag pattern. Forexample, given that the current flag pattern is 00001100 and the setflag pattern is 00000101, the current flag pattern is changed to00001101. Hereinafter, each flag pattern is defined to comprise bit 0,bit 1, . . . , and bit 7 from left to right.

A wait event system call is a system call to wait until the current flagpattern of an event to wait for fulfills a predetermined condition. Thewait event system call has an event ID, a flag pattern (hereinafter,referred to as “wait flag pattern”), and a flag condition as parameters.When a wait event system call is executed, a determination is made as towhether the flag condition is fulfilled between the current flag patternand the wait flag pattern. The flag condition is logical sum (OR) orlogical product (AND). When the flag condition is logical product (AND),the WAIT cancellation condition is that, for all bits of 1 in the waitflag pattern, the associated bits in the current flag pattern are 1.When the flag condition is logical sum (OR), the WAIT cancellationcondition is that, for at least one of bits of 1 in the wait flagpattern, the associated bits in the current flag pattern are 1. Forexample, given that the current flag pattern is 00001101, the wait flagpattern is 0000011, and the flag condition is logical sum (OR), bit 6and bit 7 of the wait flag pattern are 1 and bit 7 of the current flagpattern is 1. In this case, the WAIT cancellation condition designatedin the wait event system call is fulfilled. Meanwhile, if the flagcondition is logical product, the WAIT cancellation condition is notfulfilled since bit 6 of the current flag pattern is 0.

[1] Event Process Performed by a Commonly Used Software RTOS

The following processes are performed by a commonly used RTOS whenexecuting a wait event system call and when executing a set event systemcall. In a commonly used RTOS, an event table is maintained on thememory for event management. An event table stores not only an event ID,a current flag pattern but also the task ID of a task in the WAIT statefor the reason that the task waits for the associated event(hereinafter, referred to as a task in wait for an event), a wait flagpattern of the task, and a flag condition of the task, in associationwith each other.

<Execution of a Wait Event System Call>

A1. The RTOS reads a current flag pattern of the event designated in asystem call from the event table.

A2. The RTOS compares the current flag pattern with the wait flagpattern according to the flag condition so as to determine whether theWAIT cancellation condition is fulfilled.

(When the WAIT Cancellation Condition is Fulfilled)

A3. The RTOS causes the task that has executed the system call to make atransition from RUN to READY.

(When the WAIT Cancellation Condition is Not Met)

A3. The RTOS records the task ID of the task that has executed thesystem call in the event table.

A4. The RTOS records the wait flag pattern in the event table.

A5. The RTOS records the flag condition in the event table.

A6. The RTOS causes the task that has executed the system call to make atransition from RUN to WAIT.

<Execution of a Set Event System Call>

B1. The RTOS reads from the event table the current flag pattern, taskID, the wait flag pattern, and the flag condition associated with theevent designated in the system call.

B2. The RTOS records the logical sum of the current flag pattern and theset flag pattern as a new current flag pattern.

(When there are No Tasks in Wait for the Designated Event, or When theWAIT Cancellation Condition is Not Fulfilled in Reference to the WaitFlag Pattern and the Flag Condition Even if there is a Task in Wait forthe Designated Event).

B3. The RTOS causes the task that has executed the system call to make atransition from RUN to READY.

(When there is a Task in Wait for the Designated Event and the WAITCancellation Condition is Fulfilled)

B3. The RTOS causes the task formerly in wait for the designated eventto make a transition from WAIT to READY.

B4. The RTOS clears the wait task ID, the wait flag pattern, and theflag condition in the event table.

B5. The RTOS causes the task that has executed the system call to make atransition from RUN to READY. Also, the RTOS selects a RUN-task.

The following policies are observed when the RTOS selects a READY-taskfrom among a plurality of WAIT-tasks when a set event system call isexecuted.

1. The task selected should be a WAIT-task (first condition).

2. The task selected should be a WAIT-task in wait for an eventdesignated in the system call (second condition).

3. The task selected should be a task for which the WAIT cancellationcondition is fulfilled based upon the comparison as to the wait flagpattern, the current flag pattern, and the flag condition (thirdcondition).

These three conditions will be collectively referred to as an event waitcancellation condition.

[2] Event Process Performed by the Hardware RTOS

The following processes are performed by the RTOS when the taskprocessor 100 executes a wait event system call and when it executes aset event system call. The semaphore table 212 built in the taskprocessor 100 stores an event ID and a current flag pattern inassociation with each other. Information such as a wait task ID and await flag pattern is stored in the state storage units 220.

<Execution of a Wait Event System Call>

A1. The task-switching circuit 210 reads a current flag pattern from theevent table 214.

A2. The task switching circuit 210 compares the current flag patternwith the wait flag pattern according to the flag condition so as todetermine whether the WAIT cancellation condition is fulfilled.

(When the WAIT Cancellation Condition is Fulfilled)

A3. The circuit 210 indicates READY in the task state register 258 forthe task that has executed the system call.

(When the WAIT Cancellation Condition is Not Fulfilled)

A3. The task switching circuit 210 indicates WAIT in the task stateregister 258 for the task that has executed the system call, indicates“in wait for an event” in the wait reason register 262, sets the eventID of the event to wait for in the event ID register 266, sets the waitflag pattern in the wait flag register 268, and sets the flag conditionin the flag condition register 270.

<Execution of a Set Event System Call>

B1. The task switching circuit 210 reads a current flag pattern from theevent table 214 and feeds the event ID of the event designated in thesystem call to the event-based selection circuit 236.

B2. The task switching circuit 210 produces a logical sum of the currentflag pattern from the event table 214 and the set flag pattern.

B3. The event-based selection circuit 236 selects a task for which theevent wait condition is fulfilled with reference to the event ID thusfed. A plurality of tasks may be selected regardless of the taskpriority order and the elapsed WAIT time.

(When there is a Task that Fulfills the Event Wait CancellationCondition)

B4. The circuit 210 indicates READY in the task state register 258 forthe task in wait for the event and clears the event ID register 266, thewait flat register 268, and the flag condition register 270.

B5. The circuit 210 causes the task that has executed the system call tomake a transition from RUN to READY.

(When there are No Tasks that Fulfill the Event Wait CancellationCondition)

B4. The circuit 210 causes the task that has executed the system call tomake a transition from RUN to READY.

[Timeout Process]

The task that has made a transition to the WAIT state makes a transitionto the READY state when the WAIT cancellation condition is fulfilled. Ifthe fulfillment of the WAIT cancellation condition is thwarted due tosome external factor or a bug in an application program, the task isincapable of leaving the WAIT state. In this regard, a timeout value isnormally established when a task is caused to makes a transition to theWAIT state. A timeout value is decremented periodically. When the valuereaches 0, the task is forced to make a transition from the WAIT stateto the READY state even if the WAIT cancellation condition is notfulfilled. In this way, the task is prevented from remaining in the WAITstate for a period of time beyond the timeout value.

[1] Timeout Process Performed by a Commonly Used Software RTOS

In the case of a commonly used software RTOS, a timeout value isestablished in the TCB for a task in the WAIT state. The timeout valueis decremented periodically. The RTOS sends an interrupt to the CPUprocess periodically so as to check the entire TCBs and detect aWAIT-task for which the timeout value reaches 0. In the event that sucha task is detected, the RTOS causes the task to make a transition fromWAIT to READY.

[2] Timeout Process Performed by the Hardware RTOS

In the case of the embodiment, the task switching circuit 210 decrementsthe timeout value of the timeout counters 274 periodically. Timeoutvalues are established as a parameter in executing systems call relatedto WAIT. The task switching circuit 210 establishes a timeout value inthe timeout counter 274 for the task that has executed the system call.

Since the process of decrementing the timeout value does not require theCPU 150, the task switching circuit 210 is capable of updating thetimeout value independent of the task execution process. Therefore, thetask control circuit 200 is capable of updating the timeout valueautonomously even while the CPU 150 is executing the task. Since thestate data is continuously fed to the timeout detecting circuit 238, thetimeout detecting circuit 238 is capable of detecting a task for whichthe timeout count reaches 0 substantially at the same time as thetimeout count is updated. The timeout detecting circuit 238 outputs thetask ID of the detected task. Upon receiving the task ID from thetimeout detecting circuit 238, the task switching circuit 210acknowledges that a timeout has occurred. The circuit 210 then assertsHC so as to halt the supply of the CPU clock. The task switching circuit210 causes the WAIT-task for which the timeout has occurred to make atransition to READY and causes the RUN-task to make a transition toREADY. The task switching circuit 210 selects a task to be executed nextfrom among the READY-tasks. The task switching circuit 210 restarts thetimer 252 for the task for which the timeout has occurred so as tomeasure the elapsed READY time.

According to the method of processing described above, occurrence of atimeout during the execution of a task, i.e., while the CPU clock isrunning, is immediately followed by an interrupt to the CPU 150 for atask switch. The task switching circuit 210 is capable of independentlyupdating the timeout value during the execution of a task withoutdepending on the processing power of the CPU 150.

[Task Switching Circuit 210 as a Finite State Machine]

FIG. 15 is a state transition diagram of the task switching circuit 210.

Before an initialization process (A1), all tasks are in an IDLE state.When the initialization process is complete (S10), one of the tasksbecomes a RUN-task and the circuit 210 is placed in the task executionstate (A2). When an interrupt request signal is detected (S12), aspecial task becomes a RUN-task and an interrupt process (A3) isperformed. When the interrupt process is completed (S14), the taskswitching circuit 210 selects a RUN-task from among the ordinary tasksand makes a transition to A2.

When a system call is executed while a task is being executed (A2)(S16), a system call process is performed (A4). When a task switch,i.e., switching of RUN-tasks, does not occur (S18), the circuit 210returns to A2. When a task switch occurs as a result of a system callprocess (A4) (S20), the task switching circuit 210 selects a RUN-taskbased upon an output from the execution selection circuit 232 (A5). Whena task switch is completed (S22), the circuit 210 makes a transition tothe state A2.

Finally, an additional description will be given of cases where only oneof the save circuit 120 and the task control circuit 200, which are mainelements of the task processor 100, is implemented.

[Task Processor 100 of a Type not Provided with the Task Control Circuit200]

FIG. 16 is a circuit diagram showing a variation to the task processor100 of FIG. 5 in which the task control circuit 200 is not provided.

Instead of providing the task control circuit 200, a register switchingcontrol circuit 322 and a process data storage unit 320 are added. Sincethe processor 100 is not provided with the task control circuit 200, thetask scheduling function is implemented by the software RTOS.Accordingly, the RTOS needs to acquire the right to use the CPU 150temporarily for a task switch. Normally, the process data storage unit320 stores process data for the RTOS. When the RTOS acquires the rightto use the CPU 150, the process data storage unit 320 switches betweenthe process data for use by the RTOS stored in the unit 320 and theprocess data for use by the task stored in the special registers 156.The processing steps involved will be described assuming that task A isswitched to task B.

A1. When task A executes a system call, the parameter in a system calland the system call ID are recorded in some of the general-purposeregisters 158.

A2. The register switching control circuit 322 moves the process datafor task A to the process data storage unit 320 and loads the processdata for use by the RTOS in the process data storage unit 320 to theprocessing register set 154. At this stage, the RTOS acquires the rightto use the CPU 150.

A3. The register switching control circuit 322 feeds a write signal tothe save register 110 a so as to save, in the save registers 110, theprocess data for use by task A stored in the process data storage unit320.

A4. The RTOS performs a process responsive to the system call based uponthe parameter and ID of the system call recorded in the general-purposeregisters 158. Further, the RTOS indicates in the TCB for task A thattask A is READY and appends the TCB for task A to the task ready list.

B1. Subsequently, the RTOS selects a RUN-task (in this case, task B) inaccordance with the RUN-task selecting condition described above.

B2. The RTOS directs the register switching control circuit 322 to feeda task selection signal designating task B to the load selection circuit112. This causes the process data to be moved from the save register 110b to the process data storage unit 320.

B3. The register switching control circuit 322 switches between theprocess data for use by task B in the process data storage unit 320 andthe process data for use by the RTOS in the processing register set 154.This allows task B to acquire the right to use the CPU 150.

According to the method of processing described above, the taskprocessor 100 can be made more compact in overall size as compared tothe task processor 100 of FIG. 5 provided with the task control circuit200. The RTOS is implemented in software. However, the loading andsaving of process data are subject to hardware control according tosignals from the register switching control circuit 322. By defining thenumber of bits of the bus connecting the processing register set 154,the process data storage unit 320, the load selection circuit 112, andthe save registers 110 so as to enable parallel transfer of processdata, tasks can be switched faster than by saving process data in TCBsand loading process data from TCBs.

[Task Processor 100 of a Type not Provided with the Save Circuit 120]

FIG. 17 is a circuit diagram showing a variation to the task processor100 of FIG. 5 in which the save circuit 120 is not provided.

Instead of providing the save circuit 120, an interrupt interfacecircuit 324 is added. Since the save circuit 120 is not provided,process data is saved in TCBs in the memory. Saving and loading ofprocess data are achieved by the software-based RTOS. Therefore, theRTOS needs to acquire the right to use the CPU 15 temporarily for a taskswitch. The processing steps involved will be described assuming thattask A is switched to task B.

When a task switch is initiated by a system call, the software RTOSsaves the process data for task A in the TCB for task A. The RTOS loadsthe process data for the RTOS in the processing register set 154. Themethod of processing is similar to that described with reference to FIG.3.

The software RTOS writes the parameter of a system call in the interruptinterface circuit 324. The execution control circuit 152 halts the CPUclock of the CPU 150. The interrupt interface circuit 324 causes thetask control circuit 200 to perform a task switch. The task switchingcircuit 210 indicates READY in the task state register 258 for task Aand selects task B as the next RUN-task in accordance with an outputfrom the task selecting circuit 230. The task switching circuit 210directs the interrupt interface circuit 324 to load the process data fortask B. At this point of time, the interrupt interface circuit 324causes the execution control circuit 152 to resume the CPU clock. Theinterrupt interface circuit 324 notifies the software RTOS that task Bis selected. The software RTOS accesses the TCB for task B so as to loadthe process data for task B into the processing register set 154.

According to the method of processing described above, the taskprocessor 100 can be made more compact in overall size as compared tothe task processor 100 of FIG. 5 provided with the save circuit 120. Apart of the RTOS function is implemented in hardware but the taskselection process is implemented by the task control circuit 200.

Unlike the software RTOS described with reference to FIGS. 2 and 3, apart of the RTOS function is implemented in the hardware of the taskprocessor 100 of FIGS. 16 and 17. As described with reference to FIG.16, provision of the save circuit 120 eliminates the need to access TCBsto save and load process data. This allows the register switchingcontrol circuit 322 to save and load process data. Meanwhile, asdescribed with reference to FIG. 17, provision of the task controlcircuit 200 allows the software RTOS can delegate the task selectingfunction to the task control circuit 200.

As described with reference to FIG. 5, the task scheduling function ofRTOS can be completely built into hardware in the case of the taskprocessor 100 provided with the save circuit 120 and the task controlcircuit 200. Since there is no need to access TCBs in the memory for atask switch, the speed of a task switch is further increased. Ourexperiments show that the task processor 100 according to the embodimentoperates at a speed 100 times that of a commonly used software RTOSdescribed with reference to FIG. 3.

The invention has been described with reference illustrativeembodiments. The embodiments are intended to be illustrative only and itwill be obvious to those skilled in the art that various modificationsto constituting elements and processes could be developed and that suchmodifications are also within the scope of the present invention.

The function of the selector circuit described in the claims isimplemented by the load selection circuit 112 in the embodiment.

A skilled person would appreciate that the other functions to beachieved by the constituting elements described in the claims are alsoimplemented by the respective functional blocks described in theembodiment or the coordination thereof.

Various modes of the invention encompassed by the embodiment and thevariations thereof include:

A task processor comprising: a processing register operative totemporarily store data for execution of a task; an execution controlcircuit operative to load an instruction and an operand from a memoryinto the processing register and to execute the task according to theinstruction and operand in the processing register; a plurality of stateregisters operative to store data for respective tasks for taskscheduling and respectively associated with a plurality of tasks; a taskswitching circuit operative to switch tasks; a task selecting circuitoperative to receive state data output in parallel from the plurality ofstate registers and to select a task according to a predeterminedcondition for selection, wherein the execution control circuit transmitsa predetermined system call signal to the task switching circuit whenexecuting a predetermined system call instruction, the task selectingcircuit selects a task for execution from among tasks in a READY stateindicating that the task is executable and waits for executionirrespective of whether or not the predetermined system call occurs, thetask switching circuit switches between tasks by selecting a task to beexecuted next in accordance with an output from the task selectingcircuit occurring when the system call signal is received, saving thedata in the processing register in a predetermined storage area,updating the state data in the state register associated with the taskbeing executed from RUN, indicating that the task is being executed, toREADY, loading data associated with the selected task and formerly savedin the storage area into the processing register, and updating the statedata in the state register associated with the selected task from READYto RUN

A task selecting circuit having built-in comparison circuits connectedin multiple stages, the comparison circuits in the first stage comparingthe state data of two or more tasks according to the predeterminedcondition for selection so as to output the state data of one of thetasks to the comparison circuits in the second stage, the comparisoncircuits in the nth stage, where n is a natural number equal to orgreater than two, comparing the state data output from the plurality ofcomparison circuits in the (n−1)th stage according to the predeterminedcondition for selection so as to output the state data of one of thetasks, so that the task selecting circuit selects the task identified bythe comparison circuits in the final stage as a target for execution.

A task processor, wherein the comparison circuits in the kth, where k isa natural number, do not output the state data of any task when theinput state data does not fulfill the predetermined condition forselection.

A task processor, wherein each of the state registers stores taskpriority as part of the state data, and when a plurality of tasks are inthe READY state when tasks are switched, the task selecting circuitselects the task with the highest task priority as a target forexecution.

A task processor, wherein when a plurality of tasks are in the READYstate when tasks are switched and when a plurality of tasks are assignedthe highest task priority among the tasks, the task selecting circuitselects the task with the longest elapsed time since the task isindicated as being in the READY state as a target for execution.

A task processor, further comprising a plurality of timers respectivelyassociated with a plurality of tasks, wherein when the task switchingcircuit indicates that a task is in the READY state, the circuit startsmeasuring the elapsed time by setting the timer associated with thetask.

A task processor further comprising a semaphore information storage unitoperative to store a semaphore ID and a semaphore counter in associationwith each other, wherein in the event that the execution control circuitexecutes a wait semaphore instruction, a system call for requesting asemaphore, designating a semaphore ID, the task switching circuitdecrements the semaphore counter of the designated semaphore and updatesthe state data of the task that has executed the wait semaphoreinstruction to READY when the semaphore counter is 1 or greater, and,when the semaphore counter is 0 or smaller, the task switching circuitindicates that the state data of the task that has executed the waitsemaphore instruction is in the WAIT state, indicating that the taskcannot be executed until a predetermined condition is fulfilled, andsets the designated semaphore ID in the associated state register,indicating the ID as a condition for cancellation of the WAIT state ofthe task, and in the event that the execution control circuit executes arelease semaphore instruction, a system call for releasing a semaphore,indicating a semaphore ID, the task selecting circuit selects one of thetasks in the WAIT state waiting for the semaphore with the designatedsemaphore ID according to a predetermined condition for selection, andthe task switching circuit updates, when the task selecting circuit hasselected one of the tasks, the state data of the selected task to READY,and increments the semaphore counter of the designated semaphore whennone of the tasks is selected.

A task processor, further comprising an event information storage unitoperative to store an event ID and a first flag pattern in associationwith each other, wherein in the event that the execution control circuitexecutes a wait event instruction, a system call instruction to wait forestablishment of an event, designating an event ID and a second flagpattern, the task switching circuit updates the state data of the taskthat has executed the wait event instruction to READY when apredetermined arithmetic condition is fulfilled by subjecting the firstand second flag patterns associated with the designated event toarithmetic operation, and, when the condition is not fulfilled, the taskswitching circuit indicates the task that has executed the wait eventinstruction is in the WAIT state, indicating that the task cannot beexecuted until a predetermined condition is fulfilled, and sets thedesignated event ID and the second flag pattern in the associated stateregister, indicating the ID and pattern as conditions for cancellationof the WAIT state of the task, and in the event that the executioncontrol circuit executes a set event instruction, a system call forestablishing a first flag pattern, designating an event ID and a thirdflag pattern, the task switching circuit computes a logical sum of thefirst flag pattern and the third flag pattern associated with thedesignated event, the task selecting circuit selects a task in the WAITstate waiting for the event with the designated event ID, and when thetask selecting circuit has selected a task, the task switching circuitupdates the state of the selected task from WAIT to READY on thecondition that the predetermined arithmetic condition is fulfilledbetween the first and second flag patterns stored in the state registerfor the selected task.

A task processor, wherein each of the state registers stores a timeoutcounter as part of the state data, in the event that the executioncontrol circuit executes a system call bounded by a timeout condition,the task switching circuit updates the state data of the task that hasexecuted the system call bounded by the timeout condition to WAIT andstarts updating the timeout counter, the task selecting circuit detectsa timed-out WAIT task, and the task switching circuit up dates the statedata of the timed-out task from WAIT to READY.

A task processor further comprising a mutex information storage unitoperative to store a mutex ID and a state of acquisition of a mutex inassociation with each other, wherein in the event that the executioncontrol circuit executes a wait mutex instruction for requesting amutex, designating a mutex ID, the task switching circuit indicates thedesignated mutex as being occupied when the designated mutex is formerlyunoccupied and updates the state data of the task that has executed thewait mutex instruction to READY, and indicates, when the designatedmutex is occupied, the task that has executed the wait mutex instructionis in the WAIT state, indicating that the task cannot be executed untila predetermined condition is fulfilled, and sets the designated mutex IDin the associated state register, indicating the ID as a condition forcancellation of the WAIT state of the task, and in the event that theexecution control circuit executes a release mutex instruction, a systemcall for releasing a mutex, indicating a mutex ID, the task selectingcircuit selects one of the tasks in the WAIT state waiting for the mutexwith the designated mutex ID according to a predetermined condition forselection, and the task switching circuit sets the designated mutex asbeing unoccupied, and updates, when the task selecting circuit hasselected one of the tasks, the state data of the selected task to READY.

A task processor further comprising a plurality of save registersoperative to save data in the processing register and respectivelyassociated with a plurality of tasks, wherein the task switchingcircuit, upon receipt of the predetermined system call signal, saves, inthe save register associated with a task being executed, the data in theprocessing register, and loads data in the save register associated withthe task selected by the task selecting circuit into the processingregister.

Highly efficient task execution control in multitasking operations canbe achieved through the present invention.

1. A task control circuit coupled through signal lines to a processorwhich executes a task, comprising: a plurality of state storage units,each of the state storage units being provided for a corresponding oneof a plurality of tasks and storing state data of the corresponding oneof the tasks; a task selecting circuit selecting a task for executionaccording to the state data in the state storage units; and a taskswitching circuit updating the state data in the state storage unitswhen a system call signal is received from the processor, wherein eachof the state storage units comprises a timeout counter for storing atimeout value, the timeout counter periodically decrementing a timeoutvalue associated with the task in a WAIT state, wherein the taskselecting circuit includes a timeout detecting circuit detecting thatthe timeout value associated with the task in the WAIT state isdecremented to a predetermined value to output a task ID of a detectedtask in the WAIT state to the task switching circuit, and wherein thetask switching circuit updates the state data in a state storage unitassociated with the detected task from the WAIT state to a READY state.2. The task control circuit according to claim 1, wherein the timeoutvalue is set when the processor sends the system call signal.
 3. Thetask control circuit according to claim 1, wherein the timeout value isset in a processing register included in the processor, and wherein thetask switching circuit reads the timeout value from the processingregister.
 4. The task control circuit according to claim 1, wherein thetimeout counter updates the timeout value temporally in parallel withexecution of the task by the processor.
 5. The task control circuitaccording to claim 1, wherein the task switching circuit switchesbetween tasks for execution by: selecting a task to be executed nextfrom an output from the task selecting circuit when the system callsignal is received; saving data stored in a processing register includedin the processor into a predetermined storage area and updating thestate data in the state storage unit associated with a task beingexecuted from a RUN state to another state; and loading data for theselected task saved in the predetermined storage area into theprocessing register and changing the state data in the state storageunit associated with the selected task to the RUN state.
 6. The taskcontrol circuit according to claim 1, wherein the task switching circuithalts operation of the processor when the task ID is input from thetimeout detecting circuit.
 7. A task control device coupled throughsignal lines to a processor, the task control device, comprising: stateregisters each storing state data representing an execution state of atask; a task switching circuit controlling the execution states of thetasks; and a timeout counter, wherein when the processor executes asystem call instruction bounded by a timeout condition, the taskswitching circuit sets state data of a task that has executed the systemcall instruction bounded by the timeout condition to a WAIT state andstarts updating the timeout counter, and the task switching circuitupdates state data of a timed-out task from the WAIT state to a READYstate.